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Graphics Interchange Format  |  1998-02-10  |  47KB  |  507x486  |  4-bit (16 colors)

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OCR: Figure 8 Plug and play I/O, IRQ, and DMA configuration registers Register Descriptor Index Definitions 0x60 ROW The lower limit address bits [ 15:08] for I/O Descriptor Q. 0x61 RW The lower limit address bits [07:00] for I/O Descriptor 0. 7 0x6E The lower limit address bits [16:08] for I/O Descriptor 7. 7 Cx6F The lower limit address bits [15:08] for I/O Descriptor 7. The V/O Descriptor Register Register Descriptor Index Definition 0x70 RAW Bits [3:0} indicate interrupt level. A value O implies no interrupt selection. 0 0x71 Value indicate type of interrupt. 1 0x72 Bits [3.0] indicate interrupt level, A value O implies no interrupt selection. 1 OX72 Value indicate type of interrupt. The IRQ Descriptor Register DMA Register Descriptor Index Definition 0 0x74 Bits [2:0] indicate DMA channels. A value 4 implies no DMA selection. 1 0x75 Bits [2:0] indicate DMA channels. A value 4 implies no OMA selection. The DMA Descriptor Register

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